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A high speed scalable shift-register based on-chip serial communication design for SoC applications

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5 Author(s)
I-Chyn Wey ; Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan ; You-Gang Chen ; Chia-Tsun Wu ; Wei Wang
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In this paper, a high-speed, scalable on-chip serial transmission design is proposed to provide 2Gb/s transmission bandwidth for SoC applications. By using the dynamic control technology and the single-phase pulse-triggered TSPC shift register design, we can provide high-speed on-chip serial transmission. Moreover, the shift register design is a scalable design. By using the proposed method, we can provide 3 times wider bandwidth as compared to the prior art design (Kimura et al., 2003).

Published in:

Research in Microelectronics and Electronics, 2005 PhD  (Volume:1 )

Date of Conference:

25-28 July 2005