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Algorithms that minimize the complexity of multiplication in digital filters focus on reducing the number of adders needed to implement the coefficient multipliers. Previous works have not analyzed the complexity of each adder, which is significant in low-complexity implementation. A multiplication algorithm for low-complexity implementation of digital filters with a minimum number of full adders (NFAs) and improved speed is proposed here. The authors exploit the fact that when multiplication is implemented using shifts and adds, the adder width can be minimized by limiting the shifts of the operands to shorter lengths. The coefficient-partitioning (CP) algorithm proposed here minimizes the shifts of the operands of the adders by partitioning each coefficient into two subcomponents. The authors show that by combining three methods, the CP algorithm, an efficient coefficient coding scheme known as pseudo floating-point (PFP) representation, and the well-known common subexpression elimination (CSE), the NFAs required in each adder of the multiplier can be reduced considerably. Design examples show that the method offers an average FA reduction of 30% for finite-impulse response (FIR) filters and 20% for infinite-impulse response (IIR) filters over CSE methods.