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Power-optimal simultaneous buffer insertion/sizing and wire sizing for two-pin nets

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4 Author(s)
Ruiming Li ; Dept. of Electr. Eng., Univ. of Texas, Richardson, TX, USA ; Dian Zhou ; Jin Liu ; Xuan Zeng

This paper studies the problems of optimizing power dissipation for simultaneous buffer insertion/sizing and uniform wire sizing (BISUWS), and simultaneous buffer insertion/sizing and tapered wire sizing (BISTWS). For BISUWS, we analyze the optimal total power dissipation under the delay constraints as well as the power-delay tradeoff. For BISTWS, we study the problems of minimizing power dissipation with optimal delay constraints or with a given delay penalty. We derive optimal solutions for both cases. These solutions can be used to efficiently estimate the power dissipation for long single wires in the interconnect designs.

Published in:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  (Volume:24 ,  Issue: 12 )