By Topic

Offset and dynamic gain-mismatch reduction techniques for 10b 200ms/s parallel pipeline ADCs

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

The purchase and pricing options are temporarily unavailable. Please try again later.
5 Author(s)

This paper describes novel offset, gain-error, and clock-skew minimization techniques for required channel matching of multi-channel ADCs. The proposed adaptive closed-loop offset sampling enhances the operating speed of a parallel pipeline ADC with removed channel offsets. The 10b 200MS/s 0.13μm CMOS ADC achieves the SNDR of 55dB for a 21 MHz sinusoidal input at 200MS/S without any other offset calibration. Based on the prototype ADC evaluation, a clock-skew reduction scheme is proposed to improve further the dynamic gain mismatch between channels of parallel ADCs.

Published in:

Solid-State Circuits Conference, 2005. ESSCIRC 2005. Proceedings of the 31st European

Date of Conference:

12-16 Sept. 2005