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This paper describes a 10bit 30 MSPS CMOS analog-to-digital converter (ADC) for high-speed signal processing, especially for subsampling applications, for example digital video broadcasting over cable (DVB-C), terrestrial (DVB-T) and handheld (DVB-H) systems. The proposed pipelined ADC adopts a power efficient amplifier sharing technique, an improved gate-bootstrapping technique for a wideband SHA, a proposed stable high-swing bias circuit for a wide-swing gain-boosting telescopic amplifier. The measured differential and integral nonlinearities of the prototype in a 0.25μm CMOS technology show less than 0.4 least significant bit (LSB) and 0.85LSB respectively at full sampling rate. The ADC exhibits higher than 9 effective number of bits (ENOB) for input frequencies up to 60MHz, which is the fourfold Nyquist rate (fs/2), at 30 MS/s. The ADC consumes 60 mW from a 3-V supply and occupies 1.36 mm2.