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A cyclic analog-to-digital converter (ADC) with pixel noise and column-wise offset canceling for CMOS image sensors is presented. By adding cross connection switches to a cyclic ADC, a column-wise fixed pattern noise due to the amplifier's offset variations is greatly reduced. The proposed ADC also acts as a pixel noise canceller The ADC is optimized with respect to area and power consumption in order to allow the integration of a parallel array at the column of the image sensors. A prototype 12-bit cyclic ADC implemented using a 0.25 μm CMOS technology exhibits a 4LSB maximum integral nonlinearity (INL) and 0.9LSB maximum differential non-linearity (DNL) without calibration and 1.5mVp-p column-wise offset deviation. The ADC has 62dB signal-to-noise ratio at 1 Msample/s. The power dissipation is 0.43mW at 3.3V supplies, and the area of one channel is 0.04 × 1.2mm2.