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Side channel analysis attacks, and particularly differential power analysis (DPA), pose a serious threat to cryptographic security. This is partly because the synchronous operation of traditional cipher hardware affords a fairly good correlation between the abstract power model used during analysis and the physical circuit under attack. As opposed to this, the globally-asynchronous locally-synchronous (GALS) AES cipher circuit discussed in this paper combines operation reordering and unpredictable latencies with three asynchronous clock domains and self-varying clock cycle times. Attackers are further confused by having functional units process random dummy data when idle. The design fabricated in a 0.25 μm CMOS technology comprises 39,000 gate-equivalents, occupies approximately 1 mm2 and achieves a peak throughput of more than 256 Mb/s.