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A clock-less low-voltage AES crypto-processor

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4 Author(s)
Bouesse, G.F. ; TIMA Lab., Concurent Integrated Syst. Group, Grenoble, France ; Renaudin, M. ; Witon, A. ; Germain, F.

This paper presents a concrete evaluation of quasi delay insensitive (QDI) asynchronous logic in terms of current consumption within a wide range of supply voltages. The designed and fabricated circuit is a QDI advanced encryption standard (AES) crypto-processor, compliant with the NIST standard FIPS197. This circuit exploits fundamental properties of the QDI asynchronous logic, especially delay insensitivity, to enable relaxed operating conditions. The circuit, powered at 1.2 volt, ciphers a 128 bit data using a 128 bit key in 910 ns which corresponds to a ciphering rate of 141 Mbits per second. Due to the robustness of the clock-less QDI logic, the circuit is functional within a wide voltage range, down to 0.4 Volt. With such a low supply voltage the chip consumes 200 μA sustaining a ciphering data rate of 6.4 Mbits/s. Moreover, clock-less circuits also generate less electromagnetic noise. This work demonstrates that QDI asynchronous logic is particularly interesting in secure, low-voltage, low-power and low-noise applications. These properties are clearly suitable to address different markets such as smartcard and mobile phones.

Published in:

Solid-State Circuits Conference, 2005. ESSCIRC 2005. Proceedings of the 31st European

Date of Conference:

12-16 Sept. 2005

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