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A 15-bit 30 MS/s 145 mW three-step ADC for imaging applications

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3 Author(s)
van der Ploeg, H. ; Philips Res., Eindhoven, Netherlands ; Vertregt, M. ; Lammers, M.

A 15-bit 30 MS/s three-step ADC for imaging applications is presented with a peak-to-peak signal to rms noise ratio of 84 dB. The offsets of the residue amplifiers are independently background calibrated. The ADC is realized in single poly, 0.18 μm CMOS, measures 1.4 mm2 and dissipates 145 mW from 1.8 V and 3.3 V supplies.

Published in:

Solid-State Circuits Conference, 2005. ESSCIRC 2005. Proceedings of the 31st European

Date of Conference:

12-16 Sept. 2005

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