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A high-speed median filter VLSI using floating-gate-MOS-based low-power majority voting circuits

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2 Author(s)
Yamasaki, H. ; Dept. of Electron. Eng., Tokyo Univ., Japan ; Shibata, T.

A low-power and high-speed mixed-signal VLSI median filter has been developed. The binary search algorithm has been employed and the median filter circuit was built using majority voting circuits. As a result, small latency median search has been established. In order to achieve a low power operation, majority voting circuits of voltage mode of operation have been developed based on the floating gate MOS technology. An 8-b 41-input median filter circuit was designed and fabricated in 0.35-μm 2-poly 3-metal CMOS technology as a proof-of-concept chip and the operation was experimentally demonstrated. It was shown that more than 70% power reduction has been achieved as compared to our previous work presented in M. Yagi et al. (2003) employing current-mode MVCs, while preserving the high-speed performance achieved in the work.

Published in:

Solid-State Circuits Conference, 2005. ESSCIRC 2005. Proceedings of the 31st European

Date of Conference:

12-16 Sept. 2005