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Deep-sub-micron technology (DSM) of 0.18 micron and below enable the integration of logical circuits having more than 10 million gates. In such a DSM technology, timing constraint has become the dominant factor in the performance of VLSI. This paper discusses a novel timing driven placement technique through genetic algorithm. The proposed algorithm has a two-level hierarchical structure consisting of outline placement and detail placement. For selection control, new objective functions are introduced for improving interconnect delay, power consumption and chip area. Experimental result shows improvement of 5.8%for interconnect delay, 0.1% for power consumption and 0.8% for chip area.