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On the advantages of serial architectures for low-power reliable computations

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5 Author(s)
Beiu, V. ; Sch. of EECS, Washington State Univ., Pullman, WA, USA ; Aunet, S. ; Nyathi, J. ; Rydberg, R.R., III
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This paper explores low power reliable micro-architectures for addition. Power, speed, and reliability (both defect- and fault-tolerance) are important metrics of system design, spanning device, gate, block, and architectural levels. The analysis considers the low power needs of future systems at supply voltages comparable to threshold voltages (Vth). Theoretical analysis and simulations show a decline of the speed advantages of parallel adders when considering wire delays. These evaluations suggest that serial adders might do better for (ultra) low power operation, with redundancy for enhancing reliability. We analyze 32-bit multiplexed serial adders. The robustness when using output-wired mirrored adder (majority) gates is shown under faulty conditions. Simulations (at 180nm, 120 nm, and 70nm) identify the supply voltages where the power-delay and energy-delay products are minimized. These show that redundant serial adders are not only low power and reliable, but can trade speed for power in a wide range (by varying VDD both above and below Vth).

Published in:

Application-Specific Systems, Architecture Processors, 2005. ASAP 2005. 16th IEEE International Conference on

Date of Conference:

23-25 July 2005