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Some of the unique issues involved in testing transmitter and receiver circuits for optoelectronic-very-large-scale-integrated (OE-VLSI) applications are reviewed. In particular, the problem of testing OE-VLSI chips prior to optoelectronic device integration is outlined. Based on circuit-level approaches such as fault sensitization and novel system-level testing methodologies, the first OE-VLSI chip with testable transmitters, receivers and digital circuitry was designed in 0.35-μm CMOS. The operation of the ASIC was verified experimentally and a fault-coverage greater than 80% is obtained, for a test time in the hundreds of microseconds range. Yield improvements ranging from 10% to 25% are predicted.
Circuits and Systems II: Express Briefs, IEEE Transactions on (Volume:52 , Issue: 11 )
Date of Publication: Nov. 2005