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A novel fault detection and diagnosis technique named the 'ping-pong' type approach for field programmable gate arrays (FPGAs) is proposed in the paper. The authors first derive efficient (k+1) test configurations for a single configurable logic block (CLB) which guarantees 100% fault coverage, where k denotes the number of inputs of a lookup table (LUT). Furthermore, the whole CLB array is divided into cell groups and each group contains two cells - the master cell and the slave cell. Since both cells can be used as the test pattern generator (TPG) and the blocks under test (BUTs) at the same time, one test session is required instead of two test sessions for traditional fault detection techniques. The test complexity can then be reduced significantly. The name of the ping-pong type approach comes from the fact that, if the master cell sends a test pattern to the slave cell, the output of the slave cell is forwarded to the input of the master cell as a test pattern. By iterating this process, all cells will receive pseudo-exhaustive test patterns. The output of each cell is read out immediately after one test pattern is applied through the configuration memory readback or implicit scan circuitry. Therefore, multiple fault detection and location can be achieved easily. Since the number of test sessions is less than that for the traditional approaches, significant speedup can be guaranteed. The detection and diagnosis complexity are compared with those of other works.