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80 Gbit/s monolithically integrated clock and data recovery circuit with 1:2 DEMUX using InP-based DHBTs

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8 Author(s)
Makon, R.E. ; Fraunhofer Inst. for Appl. Solid-State Phys., Freiburg, Germany ; Driad, R. ; Schneider, K. ; Ludwig, M.
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An 80 Gbit/s monolithically integrated clock and data recovery (CDR) circuit with 1:2 demultiplexer (DEMUX) is reported. The integrated circuit (IC) is manufactured using an InP double heterostructure bipolar transistor (DHBT) technology which features cut-off frequency values of more than 220 GHz for both fT and fmax. The CDR circuit is mainly composed of a half-rate linear phase detector including an 1:2 DEMUX, a loop filter, and a voltage controlled oscillator (VCO). The 40 Gbit/s recovered and demultiplexed data for an 80 Gbit/s input signal feature a signal swing of approximately 600 mV. The extracted 40 GHz clock signal shows a phase noise of -98 dBc/Hz at 100 KHz offset frequency. The corresponding peak-to-peak jitter amounts to 1.66ps while the rms jitter is 0.37ps. The full IC dissipates 1.65 W at a supply voltage of -4.8 V.

Published in:

Compound Semiconductor Integrated Circuit Symposium, 2005. CSIC '05. IEEE

Date of Conference:

30 Oct.-2 Nov. 2005