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This paper describes a fully-differential 1-Tap decision feedback equalizer (DFE) in 0.18μm SiGe BiCMOS technology. The circuit is capable of equalizing NRZ data up to 40 Gbps. A look-ahead architecture is used with modifications to reduce complexity in the high speed clock distribution. An analog differential voltage controls the tap weights. The design is fabricated in 0.18 μm SiGe BiCMOS technology with a 160-GHz ft. It occupies an area of 1.5 mm × 1mm and operates from a 3.3 V supply with 230 mA current. It is the first feedback equalizer at 40 Gbps in silicon.
Date of Conference: 30 Oct.-2 Nov. 2005