Referenced Items are not available for this document.
A multi-processor architecture for the platform based SoC design is proposed. Dedicated FIFOs are selected as channels between processors for designing of wireless communication system. The conditions to meet the latency and the throughput requirements are also proposed with generalized equations. To demonstrate the suggested equations, an 802.11a system is analyzed. They are confirmed by simulation of SystemC transaction level modeling.
Published in:
System-on-Chip for Real-Time Applications, 2005. Proceedings. Fifth International Workshop on
Date of Conference: 20-24 July 2005
- Page(s):
- 525 - 529
- Print ISBN:
- 0-7695-2403-6
- INSPEC Accession Number:
- 8660901
- Digital Object Identifier :
- 10.1109/IWSOC.2005.43
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