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Decision feedback equalization with quarter-rate clock timing for high-speed backplane data communications

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4 Author(s)
Miao Li ; Dept. of Electron., Carleton Univ., Ottawa, Ont., Canada ; P. Noel ; T. Kwasniewski ; Shoujun Wang

Decision feedback equalization (DFE) is a popular technique to counteract inter-symbol interference (ISI) in high-speed backplane data communications. Quarter-rate clock timing for DFE circuit design is proposed to alleviate the speed requirement of the clock timing. A receiver implemented in 0.18-μm CMOS technology demonstrates 6.25Gb/s and 8Gb/s operation over a 34" FR4 backplane.

Published in:

Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)

Date of Conference:

20-24 July 2005