Low latency and power efficient VD using register exchanged state-mapping algorithm

In this paper, a new implementation of the Viterbi decoder is proposed. RE state-mapping algorithm combines TB algorithm with the RE algorithm. By updating the starting point of the state for each memory bank, the trace back operation can be eliminated. This result reduces the latency of the TB algorithm and the resource usage of RE algorithm. When the memory unit is 3, the resource usage is 6306 bits and the latency is 72 clocks. The resource usage is 74% smaller than the RE algorithm, and the latency is 34% smaller than the k-pointer even TB algorithm. The power consumption of each algorithm are also analyzed and compared. Because the resource usage is directly related to the power, the power consumption of this scheme is also reduced as stated in D. Liu and C. Svensson (1994). Actually, the estimated power consumption is about 12% smaller than the RE algorithm.