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A low area and low power programmable baseband processor architecture

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3 Author(s)
Tell, E. ; Dept. of Electr. Eng., Linkoping Univ., Sweden ; Nilsson, A. ; Liu, D.

Fully programmable radio baseband processor architecture is presented. The architecture is based on a DSP processor core and number flexible accelerators, connected via a configurable network. Design choices are motivated by the inherent properties of the baseband algorithms used in different types of radio systems. A large degree of hardware reuse between algorithms and standards, careful selection of accelerators, and low memory cost allows very area and power efficient implementation of multi-standard radio baseband processors. A demonstrator chip for 802.11 a/b/g physical layer baseband processing was manufactured in 0.18 μm CMOS. The silicon area is 2.9 mm2, including all memories.

Published in:

System-on-Chip for Real-Time Applications, 2005. Proceedings. Fifth International Workshop on

Date of Conference:

20-24 July 2005