Cart (Loading....) | Create Account
Close category search window
 

A novel clock recovery scheme with improved jitter tolerance for PAM4 signaling

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

7 Author(s)
Hyoungsoo Kim ; Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA ; Youngsik Hur ; Moonkyun Maeng ; Bien, F.
more authors

This paper introduces a novel clock recovery scheme for multilevel high speed serial data transmission. The system extracts the clock from a 10 Gb/s pulse amplitude modulated (PAM)-4 input signal. The output is non-return-to-zero (NRZ) data synchronized with the clock. Conventional methods recover the clock by over-sampling the received signal, which requires complicated circuit to implement. In contrast, the proposed method aligns the data with clock using three different transition levels of PAM4 signal. It is implemented with only a few additional blocks. We propose the scheme phase-loop-lock based CDR block with jitter reduction block in which the PAM4 signal is detected by each transition and converted to a binary signal. The proposed jitter reduction block consists of a differentiator, three comparators, monostable multivibrators and a decision block, while CDR part incorporates a phase and frequency detector, a loop filter and a voltage controlled oscillator (VCO). Due to the acquisition of each transition data, jitter is reduced and locking time for CDR is also reduced. We evaluate the system level architecture with PAM4 10 Gb/s signal and behavioral simulation.

Published in:

System-on-Chip for Real-Time Applications, 2005. Proceedings. Fifth International Workshop on

Date of Conference:

20-24 July 2005

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.