By Topic

ESD-induced internal core device failure: new failure modes in system-on-chip (SOC) designs

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

7 Author(s)
Yoon Huh ; Global Technol. Leader, Santa Clara, CA, USA ; P. Bendix ; Kyungjin Min ; Jau-Wen Chen
more authors

With MOSFET scaling, increased design complexity, and multiple system power domains, ESD failures occur in internal core areas which are not connected to external package pins. A review of the various internal core device failure mechanisms and design recommendations are presented.

Published in:

Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)

Date of Conference:

20-24 July 2005