Fast efficient algorithms for the factoring of multiple output logic functions

Factoring is a technique for converting a two-level circuit description to a logical equivalent multilevel form to achieve economy or to meet fan-in and fan-out limitations of the given technology. The authors describe efficient algorithms that transform a two-level programmable-logic-array (PLA)-like representation of a logic function into a globally optimized multilevel multiple-output switching circuit by the use of algebraic factoring. They present the results of two synthesis algorithms, which show the influence of the factoring strategy on the area and delay of the resulting circuit. The algorithms are part of the CAD system FIGARO, which supports the automatic logic and physical design of finite state machines.<>