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CMOS wavelet compression imager architecture

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2 Author(s)
Olyaei, A. ; Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada ; Genov, R.

The CMOS imager architecture implements ΔΣ-modulated Haar wavelet image compression on the focal plane in real time. The active pixel array is integrated with a bank of column-parallel first-order incremental over-sampling analog-to-digital converters (ADCs). Each ADC performs column-wise distributed focal-plane sampling and concurrent signed weighted average quantization, realizing a one-dimensional spatial Haar wavelet transform. A digital delay and adder loop performs spatial accumulation over multiple adjacent ADC outputs. This amounts to computing a two-dimensional Haar wavelet transform, with no overhead in time and negligent overhead in area compared to a baseline digital imager architecture. The architecture is experimentally validated on a 0.35 micron CMOS prototype containing a bank of first-order incremental oversampling ADCs computing Haar wavelet transform on an emulated pixel array output. The architecture yields simulated computational throughput of 1.4 GMACS with SVGA imager resolution at 30 frames per second.

Published in:

Emerging Technologies: Circuits and Systems for 4G Mobile Wireless Communications, 2005. ETW '05. 2005 IEEE 7th CAS Symposium on

Date of Conference:

23-24 June 2005