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Flexibility is a key feature in 4G telecom systems, where there is a demand for reconfigurable transceivers that can cope with multiple standards (cellular, WLAN, Bluetooth, etc.). Additionally, these transceivers should adapt to the environment (presence of received blockers or not, status of battery power levels, etc.) to minimize power consumption and optimize performance according to the needs of the customer and the desired quality of service. In addition, flexibility is required to cut the development time and cost to implement a new future standard into the 4G system. All this calls for a digitally controlled front-end architecture ("software-defined radio") with reconfigurable RF and analog baseband blocks controlled through digital programmable software. This poses serious challenges to the design of such reconfigurable yet power-efficient RF/analog blocks. For the analog-to-digital converters in the receiver, this comes down to designing a power- and area-efficient reconfigurable converter with variable bandwidth and dynamic range. The general requirements for such converters in 4G systems is described. This is then illustrated with the design of a reconfigurable continuous-time ΔΣA/D converter with a pipelined multi-bit quantizer and 1-bit feedback. The chip has been realized in a 0.18 μm CMOS technology. It has 3 different modes (20 MHz BW/58 dB SNDR, 4 MHz BW/60 dB SNDR, 0.2 MHz BW/70 dB SNDR). The chip has an active area of 0.9 mm2 and the power consumption for the most demanding mode (20 MHz/58 dB) is 37 mW.