By Topic

Reducing power dissipation of register alias tables in high-performance processors

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $33
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
G. Kucuk ; Dept. of Comput. Eng., Yeditepe Univ., Istanbul, Turkey ; O. Ergin ; D. Ponomarev ; K. Ghose

Modern microprocessor designs implement register renaming using register alias tables (RATs) which maintain the mapping between architectural and physical registers. Because of the non-trivial power that is dissipated in a disproportionately small area, the power density in the RAT is significantly higher than in some other datapath components. Mechanisms are proposed to reduce the RAT power and the power density by exploiting the fundamental observation that most of the generated register values are used by the instructions in close proximity to the instruction producing a value. The first technique disables the RAT lookup for a source register if that register is a destination of an earlier instruction dispatched in the same cycle. The second technique eliminates some of the remaining RAT read accesses, even if the source register value is produced by an instruction dispatched in an earlier cycle. This is done by buffering a small number of recent register address translations in a set of external latches and satisfying some RAT lookup requests from these latches. The net result of applying both techniques is a 30% reduction in the RAT energy with no performance penalty, little additional complexity and no cycle time degradation.

Published in:

IEE Proceedings - Computers and Digital Techniques  (Volume:152 ,  Issue: 6 )