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Test generation for embedded circuits under the transparent-scan approach

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2 Author(s)
I. Pomeranz ; Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA ; S. M. Reddy

A new test generation procedure is introduced for scan circuits under an approach called transparent-scan. The new test generation procedure targets a circuit-under-test that is embedded in a larger design (it is also applicable to an interconnection of embedded circuits). Transferring deterministic test data to the primary inputs of an embedded circuit from an external source can be expensive. This problem is alleviated as follows. The test generation procedure starts from a given input sequence Ψ that specifies the values of the original primary inputs of the circuit (the primary inputs before scan was added). In this implementation, Ψ is a random input sequence that can be generated by an on-chip test-pattern generator (e.g. a linear-feedback shift register) driving the original primary inputs of the circuit. The test generation procedure transforms Ψ into a test sequence T for the scan circuit under the transparent-scan approach by adding to Ψ the values of the scan select and scan chain inputs. These inputs are easily controllable from the primary inputs of the design.

Published in:

IEE Proceedings - Computers and Digital Techniques  (Volume:152 ,  Issue: 6 )