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Low-power design approach of 11FO4 256-Kbyte embedded SRAM for the synergistic processor element of a Cell processor

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9 Author(s)
T. Asano ; IBM Eng. & Technol. Service, Japan ; J. Silberman ; S. H. Dhong ; O. Takahashi
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The synergistic processor element is a new architecture oriented for multimedia and streaming processing. In this architecture, the memory is not a cache but a private or scratch pad memory. Such a memory is simple and needs to be high-frequency and large space in low-power. This design uses an 11 fan-out of four (11FO4), six-cycle, fully pipelined, embedded 256-Kbyte SRAM for this purpose. The design's memory is not one hard macro, but a group of custom macros physically distributed to optimize the pipeline.

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IEEE Micro  (Volume:25 ,  Issue: 5 )