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Slow-wave phase shifter model and applications

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2 Author(s)
B. Lakshminarayanan ; Dept. of Electr. Eng., South Florida Univ., Tampa, FL, USA ; T. Weller

A true time delay multi-bit MEMS phase shifter topology based on impedance-matched slow-wave CPW sections on a 500 μm, thick quartz substrate is presented. A semi-lumped model for the unit cell is derived and used in predicting the 4-bit phase shifter performance by cascading N-sections. Experimental data for a 4.6 mm long 4-bit device shows a maximum phase error of 5.5° and S11 less than -21 dB from 1-50 GHz. This multi-bit phase shifter is used in an electronically tunable TRL calibration set. It is shown via calibration comparison method that the accuracy of the tunable TRL is close to a conventional multi-line TRL calibration. A maximum error bound of 0.14 at 50 GHz is validated using a 0.3 pF capacitor on CS-5 substrate and a 100 Ω load on GaAs substrate.

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The 2005 IEEE Annual Conference Wireless and Micrwave Technology, 2005.

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