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Design and optimization of a 5 GHz CMOS power amplifier

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3 Author(s)
Yus Ko ; Dept. of Electr. & Comput. Eng., Florida Univ., Gainesville, FL, USA ; Eisenstadt, W.R. ; Paviol, J.R.

RF CMOS power amplifier is designed for WLAN 802.11a applications. The fully integrated differential power amplifier, operating in the 5-6 GHz bands, is implemented in a 0.18 μm IBM 7WL BiCMOS SiGe process using CMOS transistors. This process has seven metal layers and thin-oxide metal-metal capacitors, which are high density. As a result, the chip size as well as the cost of the complete power amplifier is reduced. The configuration of the power amplifier is a three-stage cascaded structure with a common source-common gate cascode and a 3.3 V supply voltage. The packaged power amplifier with bondwire and package models has a 22.8 dBm P1dB compression output power with a 24.1 dBm saturation output power, an overall power added efficiency of 22.6%, and a power gain of 30 dB in simulation.

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Wireless and Microwave Technology, 2005. WAMICON 2005. The 2005 IEEE Annual Conference

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