By Topic

Fast Fourier transform using linear tagged systolic array

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Sarkar, S. ; Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India ; Majumdar, A.K.

A systematic methodology for design of systolic arrays from a set of nonlinear and nonuniform recurrence equations is discussed. A novel architectural idea, which is name tagged systolic array, is introduced. A tagged systolic array uses tags for data routing among processing elements. The design methodology described broadens the class of algorithms amenable for tagged systolic array implementation. The design methodology is illustrated by deriving a tagged systolic array for the fast Fourier transform

Published in:

Computer and Communication Systems, 1990. IEEE TENCON'90., 1990 IEEE Region 10 Conference on

Date of Conference:

24-27 Sep 1990