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Equivalent circuit model of on-wafer CMOS interconnects for RFICs

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5 Author(s)
Xiaomeng Shi ; Center for Integrated Circuits & Syst., Nanyang Technol. Univ., Singapore ; Jian-Guo Ma ; Kiat Seng Yeo ; Do, A.V.
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This paper investigates the properties of the on-wafer interconnects built in a 0.18-/spl mu/m CMOS technology for RF applications. A scalable equivalent circuit model is developed. The model parameters are extracted directly from the on-wafer measurements and formulated into empirical expressions. The expressions are in functions of the length and the width of the interconnects. The proposed model can be easily implemented into commercial RF circuit simulators. It provides a novel solution to include the frequency-variant characteristics into a circuit simulation. The silicon-verified accuracy is proved to be up to 25 GHz with an average error less than 2%. Additionally, equivalent circuit model for longer wires can be obtained by cascading smaller subsections together. The scalability of the propose model is demonstrated.

Published in:

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:13 ,  Issue: 9 )

Date of Publication:

Sept. 2005

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