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Low complexity bit-parallel multiplier for GF(2m) defined by all-one polynomials using redundant representation

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3 Author(s)
Ku-Young Chang ; Inf. Security Res. Div., Electron. & Telecommun. Res. Inst., Taejeon, South Korea ; Do won Hong ; Hyun-Sook Cho

This paper presents a new bit-parallel multiplier for the finite field GF(2m) defined by an irreducible all-one polynomial. In order to reduce the complexity of the multiplier, we introduce a redundant representation and use the well-known multiplication method proposed by Karatsuba. The main idea is to combine the redundant representation and the Karatsuba method to design an efficient bit-parallel multiplier. As a result, the proposed multiplier requires about 25 percent fewer AND/XOR gates than the previously proposed multipliers using an all-one polynomial, while it has almost the same time delay as the previously proposed ones.

Published in:

Computers, IEEE Transactions on  (Volume:54 ,  Issue: 12 )

Date of Publication:

Dec. 2005

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