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Quality transition fault tests suitable for small delay defects

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2 Author(s)
M. M. Vaseekar Kumar ; Dept. of Electr. & Comput. Eng., Southern Illinois Univ., Carbondale, IL, USA ; S. Tragoudas

Compact high quality test sets to detect small delay defects can be generated using the transition fault model by insisting that events are activated and propagated only along the critical paths for each transition fault, implicitly kept in a zero-suppressed binary decision diagram. This paper shows how to implicitly generate test functions for the described high quality transition fault model. The novelty of the method relies on a multivalued algebra that is used to generate the test functions with a single circuit traversal.

Published in:

2005 International Conference on Computer Design

Date of Conference:

2-5 Oct. 2005