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Presently, architecture description languages (ADLs) are widely used to raise the abstraction level of the design space exploration of application specific instruction-set processors (ASIPs), benefiting from automatically generated software tool suite and RTL implementation. The increase of abstraction level and automated implementation traditionally comes at the cost of low area, delay or power efficiency. The standard synthesis flow starting at RTL abstraction fails to compensate for this loss of performance. Thus, high level optimizations during RTL synthesis from ADLs are obligatory. Currently, ADL-based optimization schemes do not perform resource sharing. In this paper, we present an iterative algorithm for performing resource sharing on the basis of global dataflow graph matching criteria. This ADL-based resource sharing optimization is performed over a RISC and a VLIW architecture and two industrial embedded processors. The results indicate a significant improvement in overall performance. A comparative study with manually written RTL code is presented, too.