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Physical synthesis of energy-efficient networks-on-chip through topology exploration and wire style optimization

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5 Author(s)
Yuanfang Hu ; Dept. of Comput. Sci. & Eng., California Univ., La Jolla, CA, USA ; Hongyu Chen ; Yi Zhu ; Chien, A.
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Power consumption has become one of the first order design considerations of the nano-scale VLSI designs. In this paper, we propose a methodology to synthesize energy-efficient networks-on-chip (NoCs). Our methodology features three key characters. First, we adopt a multi-commodity flow formulation to unify network topologies, physical embedding, and wire style optimizations. Second, we utilize a variety of interconnect wire styles to achieve high performance low power on-chip communication. Third, we heuristically explore a large design space of network topologies. Experiments on a homogeneous communication demand model demonstrate that for a 4 × 4 NoC with torus topology, our methodology can achieve a power saving up to 35%.

Published in:

Computer Design: VLSI in Computers and Processors, 2005. ICCD 2005. Proceedings. 2005 IEEE International Conference on

Date of Conference:

2-5 Oct. 2005