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Personal communications require wireless nodes, which can transmit and receive reliably data under huge power constraints. Higher level of integration and reduction of power consumption can be achieved using a zero-IF architecture together with a wideband BFSK modulation scheme. Unfortunately FSK techniques performances degrade sharply in the presence of frequency offset. In this paper a comparison between potentially low power BFSK architectures is presented based on high level models. In depth analysis of four potentially low power demodulators shows that the architecture, which can assure rejection of large static offset with minimum increment in hardware complexity is the ST-DFT based demodulator. This will allow great reduction in power consumption avoiding acquisition and tracking of the offset at the receiver side.
Circuit Theory and Design, 2005. Proceedings of the 2005 European Conference on (Volume:2 )
Date of Conference: 28 Aug.-2 Sept. 2005