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Design of clock generating fully integrated PLL using low frequency reference signal

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3 Author(s)
Aaltonen, L. ; Electron. Circuit Design Lab., Helsinki Univ. of Technol., Finland ; Saukoski, M. ; Halonen, K.

Systems including for example micromechanical oscillators can provide a frequency reference, which can be in the order of few kilohertz. This paper describes a design procedure for a fully integrated charge pump phase locked loop (PLL), which can utilise low reference frequencies. Noise is taken into account in the design process and simulated example of a PLL is presented. Presented theory allows the design of a fully integrated PLL in favour of either noise or power consumption.

Published in:

Circuit Theory and Design, 2005. Proceedings of the 2005 European Conference on  (Volume:1 )

Date of Conference:

28 Aug.-2 Sept. 2005