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Fixed-point implementation of a robust complex valued divider architecture

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2 Author(s)
F. Edman ; Dept. of Electroscience, Lund Univ., Sweden ; V. Owall

In this paper a fixed-point implementation of robust complex valued divider architecture is presented. The architecture uses feedback loops and time multiplexing strategies resulting in a fast and area conservative architecture. The architecture has good numerical properties and the result is accurate to less than one ulp. A combination of low latency and high throughput rate makes the architecture ideal for modern high speed signal processing applications. The complex valued divider architecture was implemented and tested on a Xilinx Virtex-II FPGA, clocked at 100MHz, and can easily be ported to an ASIC. The FPGA implementation is used as a core component in a matrix inversion implementation.

Published in:

Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005.  (Volume:1 )

Date of Conference:

28 Aug.-2 Sept. 2005