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Design techniques for high performance CMOS flash analog-to-digital converters

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2 Author(s)
Sunghyun Park ; Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA ; Flynn, M.P.

This paper reviews the limitations in the performance of CMOS flash ADCs. Methods to enhance sampling rate, such as interleaving and latch cascading, are discussed, and a method that employs inductors to improve comparator performance is presented. We also consider the benefits and trade-offs of implementing a flash ADC without a track-and-hold.

Published in:

Circuit Theory and Design, 2005. Proceedings of the 2005 European Conference on  (Volume:1 )

Date of Conference:

28 Aug.-2 Sept. 2005