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PARE: a power-aware hardware data prefetching engine

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3 Author(s)
Yao Guo ; Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA ; M. B. Naser ; C. A. Moritz

Aggressive hardware prefetching often significantly increases energy consumption in the memory system. Experiments show that a major fraction of prefetching energy degradation is due to the hardware history table related energy costs. In this paper, the authors presented PARE, a power-aware prefetching engine that uses a newly designed indexed hardware history table. Compared to the conventional single table design, the new prefetching table consumes 7-11X less power per access. With the help of compiler-based location-set analysis, it is shown that the proposed PARE design improves energy consumption by as much as 40% in the data memory systems in 70nm processor designs.

Published in:

ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005.

Date of Conference:

8-10 Aug. 2005