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Cascaded carry-select adder (C2SA): a new structure for low-power CSA design

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4 Author(s)
Yiran Chen ; Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA ; Hai Li ; Roy, K. ; Cheng-Kok Koh

In this paper we propose a novel low-power carry-select adder (CSA) design called cascaded CSA (C2SA). Based on the prediction of the critical path delay of current operation, C2SA can automatically work with one or two clock-cycle latency and a scaled supply voltage to achieve power improvement. Post-layout simulations of a 64-bit C2SA in 180nm technology show that C2SA can operate at a lower supply voltage, attaining 40.7% energy saving, while maintaining a similar (average) latency per operation (LPO) compared to standard CSA.

Published in:

Low Power Electronics and Design, 2005. ISLPED '05. Proceedings of the 2005 International Symposium on

Date of Conference:

8-10 Aug. 2005