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An 8.3GHz dual supply/threshold optimized 32b integer ALU-register file loop in 90nm CMOS

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5 Author(s)
Hsu, S.K. ; Circuits Res. Labs, Intel Corp., Hillsboro, OR, USA ; Agarwal, A. ; Roy, K. ; Krishnamurthy, R.K.
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In high performance microprocessors, integer execution cores are one of the hottest thermal spots and peak current/power delivery limiters. This paper describes a dual-supply and dual-threshold optimized 32-bit integer execution ALU and register file loop for 8.3GHz operation in 1.2V, 90nm CMOS technology. Aggressive supply/threshold scaling on the ALU and nominal supply/threshold on the register file enables up to 25% peak energy reduction without sacrificing performance or array bit-cells stability. A hybrid split-output style CVSL sequential level converter at the ALU-register file interface is also described for robust, DC power free dual-Vcc operation. The proposed sequential occupies 10% smaller area, and saves 11% active leakage power and 14% worst case switching power as compared to conventional CVSL style sequential at the same performance.

Published in:

Low Power Electronics and Design, 2005. ISLPED '05. Proceedings of the 2005 International Symposium on

Date of Conference:

8-10 Aug. 2005