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A low-power bus design using joint repeater insertion and coding

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2 Author(s)
S. R. Sridhara ; Coordinated Sci. Lab., Illinois Univ., Urbana-Champaign, IL, USA ; N. R. Shanbhag

In this paper, we propose joint repeater insertion and crosstalk avoidance coding as a low-power alternative to repeater insertion for global bus design in nanometer technologies. We develop a methodology to calculate the repeater size and separation that minimize the total power dissipation for joint repeater insertion and coding for a specific delay target. This methodology is employed to obtain power vs. delay trade-offs for 130-nm, 90-nm, 65-nm, and 45-nm technology nodes. Using ITRS technology scaling data, we show that proposed technique provides 54%, 67%, and 69% power savings over optimally repeater-inserted 10-mm 32-bit bus at 90-nm, 65-nm, and 45-nm technology nodes, respectively, while achieving the same delay.

Published in:

ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005.

Date of Conference:

8-10 Aug. 2005