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A 120nm low power asynchronous ADC

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6 Author(s)
E. Allier ; Concurrent Integrated Syst. Group, TIMA Lab., Grenoble, France ; J. Goulier ; G. Sicard ; A. Dezzani
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This paper discusses the development of a new kind of low power processing chain which dynamically adapts sampling frequency to signals. Thus, the design of an asynchronous analog-to-digital converter (A-ADC) is tackled. Its principle is based on a nonuniform sampling scheme and asynchronous technology that allow significant activity and power savings. A test chip targetting 10-bit speech applications has been fabricated using the 120nm CMOS process from STMicroelectronics. The power consumption is lower than 180/spl mu/W leading to a figure of merit two times better than those of classical Nyquist converters recently published.

Published in:

ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005.

Date of Conference:

8-10 Aug. 2005