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Measurements and modeling of intrinsic fluctuations in MOSFET threshold voltage

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12 Author(s)
Keshavarzi, A. ; Circuit Res. Lab., Intel Corp., Hillsboro, OR, USA ; Schrom, G. ; Tang, S. ; Sean Ma
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Fluctuations in intrinsic linear VT, free of impact of parasitics, are measured for large arrays of NMOS and PMOS devices on a testchip in a 150nm logic technology. Local intrinsic ρVT, free of extrinsic process, length and width variations, is random, and worsens with reverse body bias. Although the traditional area-dependent component is dominant, a significant component of the fluctuations in small devices depends only on device width or length.

Published in:

Low Power Electronics and Design, 2005. ISLPED '05. Proceedings of the 2005 International Symposium on

Date of Conference:

8-10 Aug. 2005

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