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Effectiveness of low power dual-Vt designs in nano-scale technologies under process parameter variations

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5 Author(s)
A. Agarwal ; Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA ; Kunhyuk Kang ; S. K. Bhunia ; J. D. Gallagher
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This paper explores the effectiveness of dual-Vt design under aggressive scaling of technology, which results in significant increase in all components of leakage (subthreshold, gate and junction tunneling) while having large variations in process parameters. The present way of realizing high-Vt devices results in high junction tunneling leakage compared to low-Vt, devices, which in turn may result in negligible leakage savings for dual-Vt, designs in scaled technologies. Moreover, increase in process variation severely affects the yield of such designs. This paper suggests important measures that need to be incorporated in conventional dual-Vt, design to achieve total leakage power improvement while ensuring yield. It also shows that different process options, such as metal gate work function engineering, are required to realize high-performance and low-leakage dual- Vt designs in sub-50nm technologies.

Published in:

ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005.

Date of Conference:

8-10 Aug. 2005