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We have developed a comprehensive TCAD framework that can predict the data retention time distribution of a dynamic random access memory (DRAM) chip using the information about the designed cell transistor by coupled physics-based device and statistical simulations. We estimate the cumulative distribution function of the retention time by calculating the leakage currents of a large number of DRAM cells generated by the Monte Carlo methods. The cells have different configurations in the number, locations, and energy levels of the traps that act as localized leakage sources by the extended Shockley-Read-Hall process that includes the trap-assisted tunneling and the stress-induced bandgap narrowing effects. The linear response in the leakage current of each cell to these leakage sources is obtained through the Green's function methods. As an application, we calculate the retention time distribution of a 128-Mb DRAM chip with the 0.18-μm ground rule, and verify that the simulation results agree well with the experimental data. We also study the dependence of the retention time distribution on the temperature and negative wordline bias, and discuss the impact of the gate-induced drain leakage on the tail part of the distribution.