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Comparison frequency doubling and charge pump matching techniques for dual-band ΔΣ fractional-N frequency synthesizer

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11 Author(s)
Hyungki Huh ; Sch. of Electr. Eng., Seoul Nat. Univ., South Korea ; Yido Koo ; Kang-Yoon Lee ; Yeonkyeong Ok
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The frequency synthesizer with two LC-VCOs is fully integrated in a 0.35-μm CMOS technology. In supporting dual bands, all building blocks except VCOs are shared. A current compensation scheme using a replica charge pump improves the linearity of the frequency synthesizer and, thus, suppresses spurious tones. To reduce the quantization noise from a ΔΣ modulator and the noise from the building blocks except the VCO, the proposed architecture uses a frequency doubler with a noise-insensitive duty-cycle correction circuit (DCC) in the reference clock path. Power consumption is 37.8 mW with a 2.7-V supply. The proposed frequency synthesizer supports 10-kHz channel spacing with the measured phase noise of -114 dBc/Hz and -141 dBc/Hz at 100-kHz and 1.25-MHz offsets, respectively, in the PCS band. The fractional spurious tone at 10-kHz offset is under -54 dBc.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:40 ,  Issue: 11 )

Date of Publication:

Nov. 2005

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