By Topic

A 2.4 GHz CMOS sub-sampling mixer with integrated filtering

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Pekau, H. ; Dept. of Electr. & Comput. Eng., Univ. of Calgary, Alta., Canada ; Haslett, J.W.

A sub-sampling mixer that incorporates sampling switches and hold capacitors into the parallel resonant LC load of an LNA is proposed. The noise figure of the proposed sub-sampling mixer is lower than that of a standard sampling circuit because the proposed mixer has narrow-band gain and input noise filtering properties. A novel level-shifting clock buffer with fast rise and fall times to drive the mixer sampling switches is presented. The mixer was fabricated in a 0.18 μm CMOS process and measured results are presented for an RF input frequency of 2.42 GHz and a sampling frequency of 100 MHz. With a measured noise figure of 21.8 dB, the proposed circuit shows improved performance compared to other published sub-sampling mixers.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:40 ,  Issue: 11 )